Low-Phase-Noise Negative-Resistance Oscillator Design Based on Phase-Noise Synthesis Technique

This article proposes the general phase-noise (PN) synthesis technique for negative-resistance (NR) oscillator (OSC) design. The proposed synthesis method of designing an OSC according to the required PN and various conditions will be useful to the OSC designers struggling with tradeoffs among electrical performance, cost, and size. Specifically, a new linear PN model that takes both the frequency stabilization network and the active device with series feedback into consideration is presented. The explicit relationship between PN and the filtering frequency-selective network (FFSN) is established. According to the proposed synthesis technique, the PN of an OSC can be prescribed before design, and then, the circuit can be extracted based on the given PN performance. Four different types of 4-GHz OSCs are designed based on the prescribed PN goals: −130 dBc/Hz at 1 MHz, −145 dBc/Hz at 1 MHz, −160 dBc/Hz at 1 MHz, and −130 dBc/Hz at 10 kHz. The design results of these four OSCs meet the target specifications and match well with the theoretical PN curves, demonstrating the proposed synthesis technique. In addition, the measured figure of merit (FOM) of the novel second-order SIW OSC at 4 GHz is −213.72 dBc/Hz at 100 kHz and −216 dBc/Hz at 1 MHz, showing the state-of-the-art performance among all the reported planar OSCs.