Design of High-Speed Hybrid Vedic Multiplier for DSP Application

The main component in the Digital Signal Processing (DSP) system is Multiply and Accumulate (MAC) unit and a multiplier is an essential part in the MAC unit. The MAC unit’s performance in DSP applications is heavily influenced by the characteristics of the multiplier, including its speed, area efficiency and power consumption. Optimizing these parameters is essential for achieving efficient and high-performance signal processing applications. The proposed work shows the design of a 16-bit MAC unit based on an 8-bit hybrid Vedic multiplier. The design of an 8-bit hybrid Vedic multiplier uses Kagge stone adder and a carry skip adder. The complete design is implemented in Verilog HDL.With Xilinx Vivado, synthesis and simulations were carried out. The proposed MAC unit with Hybrid Vedic multiplier provides a notable improvement in power, area, and latency compared to conventional MAC unit. Finally, it is observed that the delay time for an 8×8-bit Hybrid Vedic multiplier was 11.941ns, while it was 8.053ns for a 16-bit MAC unit Area, delay and power are significantly improved by the proposed design.