High dimensional Bayesian optimization for circuit design

Circuit design optimization and circuit sizing of complex system architectures often demand significant computational resources, effort, and time to meet the desired design specifications. Electronic design automation (EDA) tools with machine learning algorithms have recently gained much attention for optimizing complex circuits. Standard machine learning algorithms often require a large amount of data for training, whereas collecting data for circuit sizing and design optimization is expensive, which calls for data-efficient methods. In this paper, we explore the application of Bayesian optimization (BO), a sequential data-efficient approach combined with a weighted figure of merit metric, to tackle the challenges of circuit optimization. Further, we investigate the performance of high-dimensional Bayesian optimization technique as the dimensionality of parameter space increases. We also compare the performance of the Bayesian method against the genetic algorithm. Empirical results demonstrate that Bayesian methods achieve near-optimal results with a low training budget and significantly reduce the time required compared to manual methods.