Electromigration Failure Characterization Using Laser-Induced Nonuniform Heating

Very-large-scale integration (VLSI) technology scaling has resulted in a substantial rise in power density within a chip. This leads to thermal nonuniformity across integrated circuits (ICs) impacting electromigration (EM), which occurs due to dislocation of conducting elements of interconnects caused by electron flow. Detecting EM risk by accelerated stress methods is an active area of research. This article describes a technique that uses laser to create concentrated area of high temperature, or hot spot. The high temperature is applied to targeted areas of the specific circuit or intellectual property (IP) block of a product, while the rest of the chip continues to operate at standard conditions. The notable benefit from this technique is the capability to selectively accelerate the stressing (EM) process of an individual IP block, rather than stressing the entire chip uniformly.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-03-31
DOI
https://doi.org/10.1109/ted.2025.3549743
Primary Topic
Copper Interconnects and Reliability
Type
article
Field-Weighted Citation Impact
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article

Electromigration Failure Characterization Using Laser-Induced Nonuniform Heating

B. Ajdari, Srijita Patra, Ratnesh Kumar, Ricardo Ascázubi
IEEE Transactions on Electron Devices
Copper Interconnects and Reliability
article

Electromigration Failure Characterization Using Laser-Induced Nonuniform Heating

B. Ajdari, Srijita Patra, Ratnesh Kumar, Ricardo Ascázubi
article en

Abstract

Very-large-scale integration (VLSI) technology scaling has resulted in a substantial rise in power density within a chip. This leads to thermal nonuniformity across integrated circuits (ICs) impacting electromigration (EM), which occurs due to dislocation of conducting elements of interconnects caused by electron flow. Detecting EM risk by accelerated stress methods is an active area of research. This article describes a technique that uses laser to create concentrated area of high temperature, or hot spot. The high temperature is applied to targeted areas of the specific circuit or intellectual property (IP) block of a product, while the rest of the chip continues to operate at standard conditions. The notable benefit from this technique is the capability to selectively accelerate the stressing (EM) process of an individual IP block, rather than stressing the entire chip uniformly.

IEEE Transactions on Electron DevicesVol. 72(5)
Intel (United States) (US), Iowa State University (US)
Climate action
Openalex Percentile: Top 96%
Copper Interconnects and Reliability
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