Analysis of Vedic Multipliers Using Various Adders and Reversible Logic - Review

Multiplication is one of the main functions of a digital signal processing system. The performance of the multiplier impacts the total performance of the DSP system. Thus, setting up the necessary infrastructure for the prompt and efficient installation of multipliers is essential. Vedic mathematics can help make difficult-to-solve complex situations easier to understand. The multiplication algorithm is called Urdhva Triyagbhyam in Vedic mathematics. These days, reversible logic is widely used in a wide range of applications, including optical data processing, multipliers, low-power CMOS circuits, and quantum circuits. Vedic mathematics mixed with reversible logic yields powerful multipliers. Using reversible logic in conjunction with well-known logical concepts such as basic adders and parallel prefix adders. Registers are organized in a pipeline to further accelerate the computation of multiplication. N-bit adders and N/2 Vedic multipliers come together to generate the N-bit Vedic multipliers. The designs are simulated and synthesized with Xilinx and the EDA tool after being programmed in Verilog HDL. In terms of speed, the Vedic multipliers function better.