Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory

This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10{^{{7}}}~I_{1}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{0}$ </tex-math></inline-formula> sense current ratio) and prolonged retention. The memory is enabled by the bistable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{D}$ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{G}$ </tex-math></inline-formula> transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~45$ </tex-math></inline-formula> ns at T < 10 K and cycling endurance surpassing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{9}$ </tex-math></inline-formula> cycles while maintaining the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{1}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{0}$ </tex-math></inline-formula> memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.