Design of TDI Imaging Sensor Pixel for Low Power Consumption and High-Speed Applications

In this letter, a novel high-speed, low-power consumption, large full well capacity (FWC), charge-domain Time-Delay Integration (TDI) image sensor based on a 90nm CCD-in-CMOS process is presented. A combination of the advantages of the buried channel in the CCD channel and the pinning voltage gradient in the fully depleted tapered Pinned-Photodiode (PPD) makes the proposed new structure well-suited for low-power and high-speed applications. To demonstrate the effectiveness of both optimizations, a Back-Side Illumination (BSI) test chip with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$14~\mu $ </tex-math></inline-formula>m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 14~\mu $ </tex-math></inline-formula>m pixel is designed, manufactured, and characterized. The pixel maximum FWC exceeds 120 ke−. Thanks to the built-in electric field in the tapered PPD, the test chip achieves 99.998% Charge Transfer Efficiency (CTE) under equivalent 2.5 MHz line frequency condition without Modulation Transfer Function (MTF) degradation.