Reliable multi-level cell programming in FeFET arrays for in-memory computing

Abstract With the increasing demands of AI and edge computing, traditional computing architectures face challenges in efficiency and scalability. This paper explores the use of multi-level cell FeFET arrays for in-memory computing systems, highlighting a program/verify scheme to precisely control threshold voltages (VT). Our study demonstrates the ability of a 1k FeFET crossbar to achieve up to seven distinct VT states, allowing nearly 3-bit storage per cell. This approach maintains computational accuracy and enhances storage density, offering a viable solution for energy-efficient, high-performance memory architectures.