ADPO: Adaptive DRAM Controller for Performance Optimization

Emerging applications like deep neural networks require high off-chip memory bandwidth and low dynamic loaded Double Data Rate SDRAM (DDR) latency. However, under the stringent physical constraints of chip packages and system boards, it is extremely expensive to further increase the bandwidth and reduce the dynamic loaded latency of off-chip memory in terms of DDR devices. To address the latency issues in DDR subsystems, this paper presents a novel architecture aiming at achieving latency optimization through a use case sensitive controller. We propose a reevaluation of conventional decoupling mechanisms and quasi-static arbitration methods in the DDR scheduling architecture. The adaptive scheduling algorithms offer significant advantages in various real-world scenarios. The research methodology involves implementing a rank-level timing aware read/write turnaround arbiter and setting read/write queue thresholds and read/write turnaround settings based on observed patterns. By implementing the arbiter and dynamically adjusting these parameters, the proposed architecture aims to optimize the performance of the DDR subsystem. To validate the effectiveness of the architecture, we conduct multiple experiments. These experiments evaluate the performance of the DDR subsystem under various workloads and configurations. The results demonstrate that the adaptive scheduling algorithms have advantages in achieving DDR performance attributes for workloads and improving system performance. The experimental results provide evidence of the architecture's effectiveness in reducing latency by around 10% to 50% in various real-world scenarios.