The Planar Core–Shell Junctionless MOSFET
The core-shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters.
Authors
- S. Cristoloveanu (ORCID: https://orcid.org/0000-0002-3576-5586)
- Tianchun Ye (ORCID: https://orcid.org/0000-0002-2384-9037)
- Binhong Li (ORCID: https://orcid.org/0000-0003-1215-0578)
- Yong Xu (ORCID: https://orcid.org/0000-0002-6800-234X)
- Yanguang Yu (ORCID: https://orcid.org/0000-0002-1541-9061)
- Huabin Sun (ORCID: https://orcid.org/0000-0002-8465-7151)
- Shujian Xue (ORCID: https://orcid.org/0000-0002-0525-0207)
- Fanyu Liu (ORCID: https://orcid.org/0000-0002-6154-4971)
- Yun Wang (ORCID: https://orcid.org/0000-0002-5854-9595)
- Jing Wan (ORCID: https://orcid.org/0000-0002-6339-4006)
- Xing Zhao
- Weijia Song
- Zhiyu Tang
- Cunhua Dou
- Xuan Zhang (ORCID: https://orcid.org/0009-0008-6030-0570)
Institutions
- Chinese Academy of Sciences (CN)
- Fudan University (CN)
- Nanjing University of Posts and Telecommunications (CN)
- Institute of Microelectronics (CN)
Publication Details
- Journal
- Micromachines
- Published
- 2025-03-31
- DOI
- https://doi.org/10.3390/mi16040418
- Citations
- 3
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 2.19