Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors

The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions. • Role of Defects in Device Variability : a. The study focuses on charge trapping at oxide and interface defects, which influence transistor characteristics, such as variability and reliability; b. Analysis highlights how defects manifest as discrete current steps (random telegraph noise, RTN) in nanoscale devices. • Body Bias as a Control Parameter : a. The application of body bias significantly aKects time-zero variability and time-dependent behavior of defects; b. Forward body bias (FBB) reduces variability by modulating the channel depletion region, while reverse body bias (RBB) increases it, providing design flexibility for specific applications. • Experimental Methodology a. An extended measure-stress-measure (eMSM) technique was employed for precise defect analysis; b. Measurements were conducted on nMOS and pMOS devices, revealing diKerent impacts of BB on each type. • Statistical Analysis of Defects and Step-Height Distributions a. Step heights of threshold voltage shifts were statistically analyzed, showing distinct distributions for nMOS (bimodal) and pMOS (unimodal) devices; b. A strong correlation between BB and defect impact was observed, with forward bias reducing and reverse bias enhancing variability. • Benefits for Analog Design a. The BB and FBB can be strategically used to optimize device reliability and circuit performance by tuning threshold voltage variability and reducing noise;