A Low Overhead Double‐Node‐Upset Self‐Recoverable Latch Based on Polarity Design and Source Isolation Technology

ABSTRACT With the advancement of nanotechnology and the continuous reduction in transistor dimensions, the impact of double‐node‐upset (DNU) is intensifying. This paper introduces a novel low overhead DNU self‐recoverable latch (LODSL). The LODSL latch uses polarity design and source isolation technology to reduce the number of sensitive nodes. The latch does not adopt the redundant design, reduces the circuit overhead and area, adopts D to Q transmission pathway and clock gating technology, and has the characteristics of low power consumption and low delay. Simulation results indicate that, in comparison to the recent DNU self‐recoverable latch design, the LODSL latch has achieved an average reduction of 50.8% in power consumption, 40.3% in delay, 35.6% in area, and 79.4% in power‐delay‐area product (PDAP), and it still has good robustness under different PVT conditions.