Trench-Gate Bipolar Transistor With Partially Buried Carrier Storage Layer for Enhanced Blocking and Switching Characteristics

In this work, an insulated gate bipolar transistor (IGBT) with partially buried carrier storage (PBCS) layer is proposed and studied. By embedding the highly doped carrier storage (CS) layer into the base region, the electric field intensity near the CS layer is reduced, thus avoiding the breakdown voltage (BV) drop that occurs in conventional carrier stored trench-gate bipolar transistor (CSTBT) devices. The simulation results suggest that the doping concentration of the CS layer in the proposed PBCS device is increased to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6 \times 10^{{17}}$ </tex-math></inline-formula> cm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^{-{3}}$ </tex-math></inline-formula>, and the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}$ </tex-math></inline-formula>) is lowered by 0.1 V without degrading the BV. At the same time, the Miller capacitance is reduced by 39% due to the lower silicon doping concentration at the bottom of the trench gate. Besides, by combining the CS layer region with additional hole-extracting channels, the device switching characteristics are significantly improved with 15% and 13% reduction in turn-on and turn-off loss, respectively. The proposed PBCS device is fully compatible with the existing IGBT manufacturing process, which paves promising pathways for future high-performance power electronic device applications.