Energy Efficient Compact Approximate Multplier for Error-Resilient Applications

Abstract: This study focuses on enhancing system performance through approximate computing by proposing efficient 8- transistor and 20-transistor 4:2 compressors for approximate multipliers. These designs leverage CMOS technology with constant and conditional approximation techniques to minimize errors while eliminating the need for an error recovery module. The 20-transistor compressor achieves higher accuracy at a slight area cost, while the proposed multiplier demonstrates a 50% reduction in area and a 93% improvement in power-delay-product compared to exact multipliers