A D-Band Low-Noise Amplifier With <i>Gm</i> -Boosting Technique Based on Asymmetric Coupling

This brief presents a D-band low noise amplifier (LNA) in a 40 nm bulk CMOS process. The proposed LNA includes five stages of single-ended common-gate amplifiers. The input and interstage matching networks are realized by asymmetric transformers, which effectively enhance the equivalent transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(g_{m})$ </tex-math></inline-formula> of the subsequent transistor. The asymmetric transformer features the segmented structure, offering enhanced design flexibility, and exhibits characteristics of low loss and low parasitic parameters, enabling broadband matching. Leveraging the asymmetric transformer, the LNA achieves simultaneous matching of impedance and noise. The measured power gain is 18.4 dB, with a 3-dB bandwidth of 26.8 GHz from 139.9 to 166.7 GHz. Within the effective bandwidth, the measured minimum noise figure is 5.7 dB. The LNA operates with a power consumption of 17.3 mW under a 0.9 V supply, featuring a total area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.184~{\mathrm {mm}}^{2}$ </tex-math></inline-formula> and a core area of 0.062 mm2.