An Area-Energy-Efficient 64–2048 Point FFT With Approximate Plane-Fitting Complex Multipliers

As a key component of fast Fourier transform (FFT), the complex multiplier (CM) includes twiddle factor generation and corresponding multiplication. This brief proposes an tailored approach for approximating CM functionality by employing an adapted piecewise-plane-fitting technique, effectively replacing the conventional look-up-table-based twiddle generation and exact multipliers by shift-and-add calculation. Numerical binary calculation analysis and simulations are conducted to achieve an optimal tradeoff among accuracy, circuit complexity, power, and delay. Based on 45-nm CMOS, logic synthesis results demonstrate significant improvements, with area, power, and delay reductions of 64.18%, 64.98%, and 19.77%, respectively. With optimizations on logic structures, the complete design of the 64–2048 point FFT has efficiently adopted the proposed CM with evident improvement. The proposed FFT outperforms other reconfigurable FFT designs in terms of normalized area reduction over 55.53% and normalized energy improvement over 21.51%. In field-programmable gate array (FPGA) implementation, the proposed FFT has significantly more savings compared with the exact FFT. In practice, the approximate FFT output results’ PSNR ranges from 56 to 83 dB with competent accuracy in typical signal processing.