OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis
This article introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine-learning (ML) applications within the logic synthesis process. Previous dataset generation flows were tailored for specific tasks or lacked integrated ML capabilities. While OpenLS-DGF supports various ML tasks by encapsulating the three fundamental steps of logic synthesis: 1) Boolean representation; 2) logic optimization; and 3) technology mapping. It preserves the original information in both Verilog and ML-friendly GraphML formats. The Verilog files offer semi-customizable capabilities, enabling researchers to insert additional steps and incrementally refine the generated dataset. Furthermore, OpenLS-DGF includes an adaptive circuit engine that facilitates the final dataset management and downstream tasks. The generated OpenLS-D-v1 dataset comprises 46 combinational designs from established benchmarks, totaling over 966 000 Boolean circuits. OpenLS-D-v1 supports integrating new data features, making it more versatile for new tasks. This article demonstrates the versatility of OpenLS-D-v1 through four distinct downstream tasks: circuit classification, circuit ranking, quality of results (QoR) prediction, and probability prediction. Each task is chosen to represent essential steps of logic synthesis, and the experimental results show the generated dataset from OpenLS-DGF achieves prominent diversity and applicability. The source code and datasets are available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/Logic-Factory/ACE/blob/master/OpenLS-DGF</uri>.
Authors
- Rui Wang (ORCID: https://orcid.org/0000-0002-6298-0716)
- Xingquan Li (ORCID: https://orcid.org/0000-0002-7145-9391)
- Zhufei Chu (ORCID: https://orcid.org/0000-0001-5718-4822)
- Guojie Luo (ORCID: https://orcid.org/0000-0003-4932-3655)
- Xiaoze Lin (ORCID: https://orcid.org/0000-0001-7512-5746)
- Junfeng Liu (ORCID: https://orcid.org/0009-0006-8205-4564)
- Weikang Qian (ORCID: https://orcid.org/0000-0002-5129-9431)
- Xingyu Meng (ORCID: https://orcid.org/0000-0001-5787-0101)
- Liwei Ni (ORCID: https://orcid.org/0009-0003-7525-9375)
- Miao Liu (ORCID: https://orcid.org/0000-0002-3372-9186)
- Huawei Li (ORCID: https://orcid.org/0000-0001-8082-4218)
- Biwei Xie (ORCID: https://orcid.org/0000-0003-4045-6806)
- Xiaoyan Yang
Institutions
- Ningbo University (CN)
- Shenzhen University (CN)
- Shanghai Jiao Tong University (CN)
- Chinese Academy of Sciences (CN)
- Peking University (CN)
- Institute of Computing Technology (CN)
- Peng Cheng Laboratory (CN)
- University of Chinese Academy of Sciences (CN)
- Hangzhou Dianzi University (CN)
Publication Details
- Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2025-03-28
- DOI
- https://doi.org/10.1109/tcad.2025.3555506
- Citations
- 2
- Primary Topic
- Formal Methods in Verification
- Type
- article
- Field-Weighted Citation Impact
- 3.01
Funders
- National Natural Science Foundation of China