Placement Refinement Strategies for Security Closure

The security closure of integrated circuits (ICs) is an emerging area of research within the very large scale integration (VLSI) community. Malicious third parties, referred to as “attackers,” can employ various techniques to leak, alter, or manipulate the logic of a circuit. When targeting a completed layout, their primary goal is often the insertion of hardware trojans. In this work, we present algorithms that strengthen placement solutions against hardware trojan attacks. While state-of-the-art methods rely on exhaustive placement algorithms, we propose a clustering-based placement approach that reduces the number of moved cells by up to 17%. Additionally, we introduce a cell movement heuristic aimed at preventing increases in wirelength. Our methods reduce vulnerable placement sites by up to 78% while maintaining minimal impact on design performance. Compared to other approaches, our solution decreases the amount of moved cells to an average of 8%, mitigating the impact on wirelength to an average of 0.5%.