A Novel In-Memory Reconfigurable Magnitude Comparator Using STT-MRAM

Large-scale data applications often encounter substantial energy consumption due to frequent transfers between memory and processing units. In-memory computing (IMC) addresses this issue by executing operations directly in memory, reducing data movement and boosting both processing speed and energy efficiency. IMC which employs non-volatile devices and modified architecture provides an effective approach for creating high-performance computing systems while reducing resource requirements. We introduce a novel comparator that exemplifies the synergistic potential of these technologies in addressing power efficiency and performance challenges. This comparator is designed with a modified array architecture that employs spin-transfer torque magnetic random access memory (STT-MRAM) bit-cells and their associated peripherals are capable of performing a 1-bit comparison in a single read cycle, making it crucial for applications within the communication industry. This design demonstrates improved reconfigurability, memory cell efficiency, and computational cycles without significantly increasing other parameters compared to existing designs. This work also introduces several key innovations: 1) a modified decoder architecture that provides a unique method for activating word lines; 2) two distinct approaches for read termination are proposed, utilizing a serial-in-serial-out (SISO) register and a mod-counter for enhanced efficiency; and 3) furthermore, both 1-bit and 4-bit comparators have been implemented, with their functionalities validated through simulation tests. Additionally, this design approach can be extended to n-bit comparators, requiring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n+1$ </tex-math></inline-formula> computation cycles in the worst case scenario of input combinations while utilizing only four magnetic tunnel junction (MTJ) memory cells within the array. With minor adjustments to the peripheral circuitry, this methodology demonstrates impressive efficient performance.