A Method for Clock Domain Crossing Analysis of VHDL Code Based on Static Analysis

As the scale and complexity of digital logic design continue to grow, the probability of clock domain crossing problem increases. Meanwhile the detection of these problems is becoming increasingly difficult. A static analysis-based method for analyzing clock domain crossing problem in VHDL code is presented in this paper. First the VHDL code is parsed to generate an abstract syntax tree (AST). Then the AST is analyzed and traversed to construct a clock tree. The clock domains of signals are inferred in this process, and ultimately, the clock domain crossing paths are identified. Clock domain crossing problem within VHDL code are automatically detected by this method, which reduces the workload associated with manual code review and enhances the efficiency of digital logic verification.