Single event effects in stacked complementary multi-gate FET logic inverters

Abstract The soft errors due to the heavy ion strikes in MOSFETs are major reliability threats in VLSI circuits. The capture rate of these soft errors in integrated circuits increases with the frequency of the circuits. In order to predict and mitigate the soft errors in sub-50 nm MOSFETs, it is essential to analyze the transient effects due to the ion strikes in nano-scaled devices and the resultant perturbations in the circuit characteristics. In this paper, the single event transients (SET) in multi-gate FETs (MG-FETs) such as FinFET, inserted-oxide FinFET (i-FinFET) and nano-wire FET (NWFET) due to the heavy ion strikes and the output voltage perturbations of the complementary MG-FETs are analyzed. The transient current in these chosen devices are plotted for different linear energy transfer (LET), strike angles, strike positions in the channel, doping concentration and drain voltages. It is observed from the simulation results that the NWFET shows better immunity to the radiation effects. Further, the effect of ground plane below the buried oxide (BOX) in NWFET on the SET current is analyzed and observed that the device with ground plane are radiation tolerant. The output voltage perturbations in complementary MG-FETs due to ion strike and the corresponding SET pulse width variations in FinFET, i-FinFET and NWFET as NMOS devices are analyzed through TCAD mixed-mode simulations.