The Electrical Characterization of TeO₂-based Metal-Oxide-Semiconductor Devices

In this study, an Al/TeO 2 /p-Si metal/oxide/semiconductor (MOS) structure was fabricated using tellurium oxide (TeO 2 ) via thermal evaporation. The tellurium oxide layer coated on the p-Si oxide substrate was examined by X-ray diffraction, the formation of both TeO 2 and Te 2 O 5 oxide layers was observed, and the orientations of the related structures were determined. The electrical characterization of the Al/TeO 2 /p-Si (MOS) structure was performed at room temperature under dark conditions using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The ideality factor (n) was found to be 1.55, with a zero-bias barrier height ( Φ B ) of 0.76 eV as determined from I-V characteristics. Deviations from ideality were attributed to oxide interfacial films at the Al/p-Si junction, interfacial state distributions, and the high series resistance in the neutral region of the p-Si semiconductor layer. The Norde and Cheung methods were employed to analyze the series resistance. Additionally, frequency-dependent variations in C-V and conductance-voltage were analyzed for the Al/TeO 2 /p-Si (MOS) structure. Comparative analysis with existing literature supports the conclusion that tellurium oxide (TeO 2 ) holds promise as an alternative to silicon oxide in device technology.