A Co-Optimization Method for Analog IC Placement and Routing Based on Sequence Pairs and Random Forests

In the physical design of integrated circuits (ICs), conventional methodologies treat placement and routing as two sequential and independent steps, resulting in placement adjustments that do not sufficiently account for routing requirements. Such decoupled optimization leads to various routing challenges, including congestion and excessive wirelength. To address these limitations, we propose a novel iterative co-optimization framework that simultaneously considers placement and routing. Our methodology establishes an interdependent relationship between placement and routing, where routing is guided by the placement results and placement is adaptively adjusted based on the routing feedback. The proposed framework comprises two key components. First, we introduce an efficient gridless routing algorithm based on line exploration, which rapidly generates routing results by leveraging the placement state and netlist connectivity. The routing connectivity ratio and wirelength are then incorporated as the primary optimization metrics for placement refinement. Second, we develop an advanced placement optimization algorithm that integrates random forest techniques with Monte Carlo-based optimization. This algorithm systematically integrates routing information to guide iterative placement refinement, with the goal of achieving a higher routing connectivity ratio and a reduction in wirelength. We evaluated our approach on a dataset provided by Empyrean. Compared to the baseline placements in the dataset, the algorithm proposed in this work achieved an average improvement of 8.03% in terms of routing connectivity ratio and an average reduction of 18.33% in wirelength. Additionally, a comparative analysis of four optimization algorithms under the proposed co-optimization framework and the traditional half-perimeter wirelength (HPWL) method reveals achieved improvements of 12.41%, 14.16%, 13.87%, and 14.02% in the routing connectivity ratio, respectively, significantly outperforming the HPWL-based method. These results substantiate the efficacy of our co-optimization approach in enhancing IC physical design outcomes.