A Wide Range Integer‐N PLL With Fast Frequency Settling Techniques for Multi‐Standard Applications

ABSTRACT This letter proposes a ring‐VCO‐based integer‐N phase‐locked loop (PLL) with a wide frequency output range and fast frequency transitions for multi‐standard applications. To reduce power consumption, two key techniques are introduced. First, a VCO gain calibration unit calibrates the variable resistor‐based V‐to‐I converter, ensuring a consistent frequency tuning slop under process, voltage and temperature (PVT) variations. Second, a pulse‐swallow divider and timing control unit suppress unnecessary frequency fluctuation and achieve fast phase locking. This design enables PLL to reach the target frequency with 500 ns even under PVT variations. The proposed PLL covers 850 MHz to 3.3 GHz, achieving −107.3 dBc/Hz phase noise at a 10 MHz offset, with 6 mW power consumption at 3.3 GHz and an active area of 0.09 mm 2 .