A V<sub>M</sub>-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces

This paper introduces a three-level pulse amplitude modulation single-ended transmitter using V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> (half of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {DDQ}}$ </tex-math></inline-formula>) termination, designed for next-generation low-power memory interfaces. The proposed signaling strategy, based on the V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> termination, improves signal integrity by reducing signaling current by 41.05% while maintaining the same voltage swing compared to existing V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub>-terminated structures for low-power memory interfaces. This reduction in signaling current effectively decreases simultaneous switching output noise. Additionally, this approach alleviates the voltage headroom limitation and enables pre-emphasis adoption, resulting in a larger voltage swing and reduced power consumption compared to de-emphasis. The voltage difference between the drain and source of each pull-up and pull-down driver is balanced, achieving a good ratio of level mismatch (RLM). Moreover, the three-step ZQ calibration and transmission gate-based receiver-side V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> termination help achieve accurate on-resistance and improve output linearity, reducing signal reflection. The prototype chip, fabricated using a 65-nm CMOS process, has an area of 0.0184 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. It achieves a data rate of 22.5 Gb/s with an energy efficiency of 0.86 pJ/bit and a measured RLM of 99.2%.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-03-27
DOI
https://doi.org/10.1109/tcsi.2025.3552405
Citations
5
Primary Topic
Semiconductor materials and devices
Type
article
Field-Weighted Citation Impact
3.65
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article

A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces

Joo‐Hyung Chae, Ki-Soo Lee, Juncheol Lee, Chanheum Han
5 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Semiconductor materials and devices
3.65
article

A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces

Joo‐Hyung Chae, Ki-Soo Lee, Juncheol Lee, Chanheum Han
article en
5 citations

Abstract

This paper introduces a three-level pulse amplitude modulation single-ended transmitter using V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> (half of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {DDQ}}$ </tex-math></inline-formula>) termination, designed for next-generation low-power memory interfaces. The proposed signaling strategy, based on the V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> termination, improves signal integrity by reducing signaling current by 41.05% while maintaining the same voltage swing compared to existing V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub>-terminated structures for low-power memory interfaces. This reduction in signaling current effectively decreases simultaneous switching output noise. Additionally, this approach alleviates the voltage headroom limitation and enables pre-emphasis adoption, resulting in a larger voltage swing and reduced power consumption compared to de-emphasis. The voltage difference between the drain and source of each pull-up and pull-down driver is balanced, achieving a good ratio of level mismatch (RLM). Moreover, the three-step ZQ calibration and transmission gate-based receiver-side V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> termination help achieve accurate on-resistance and improve output linearity, reducing signal reflection. The prototype chip, fabricated using a 65-nm CMOS process, has an area of 0.0184 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. It achieves a data rate of 22.5 Gb/s with an energy efficiency of 0.86 pJ/bit and a measured RLM of 99.2%.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 72(6)
Kwangwoon University (KR)
Affordable and clean energy
Openalex Percentile: Top 7%
Semiconductor materials and devices
3.65
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