A Compact and Low-Loss D-Band SPDT Switch Using 65-nm CMOS Technology

A compact CMOS single-pole double-throw (SPDT) switch employing a parallel configuration of shunt transistors is proposed to achieve low insertion loss in the D-band. The parallel configuration of switching transistors, which reduces the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-resistance of the active transistor, inherently enhances the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state isolation in the proposed SPDT switch employing shunt transistors. Additionally, the increased <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-capacitance of the inactive shunt transistors in this configuration reduces insertion loss by effectively shortening the transmission line through increased capacitive loading. The proposed SPDT switch was fabricated using a 65-nm bulk CMOS process, achieving a compact core chip area of 0.03 mm2. Measurement results demonstrate an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state insertion loss of 1.7 dB and an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state isolation of 18 dB at an operating frequency in the D-band. The simulated input <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {1 dB}}$ </tex-math></inline-formula> at 150 GHz is 15 dBm.