A <i>V</i>-Band Divide-by-6 Injection-Locked Frequency Divider Using Current-Reused Topology With Second Injection and Harmonic Boosting

This letter presents a V-band injection-locked frequency divider (ILFD) with high input sensitivity and wide locking range (LR), implemented in 90-nm CMOS technology. The proposed divide-by-6 ILFD employs a modified current-reused topology with second injection and harmonic boosting to enhance the overall LR while maintaining high sensitivity. This architecture consists of two stages: a front-stage divide-by-2 ILFD, followed by a back-stage divide-by-3 ILFD. At an input power of 0 dBm, the measured maximum LR reaches up to 8.1 GHz, covering frequencies from 54.7 to 62.8 GHz. This design achieves the highest LR <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times {n}$ </tex-math></inline-formula> and has comparable figure of merits (FoMs) among the reported CMOS microwave and millimeter-wave (mm-wave) ILFDs, when operated at lower input powers. Notably, this proposed ILFD offers a unique combination of features: wide LR with a low dc power consumption of 12.2 mW, competitive input sensitivity, and a high division ratio up to six.