Systematic CXL Memory Characterization and Performance Analysis at Scale

Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (SPA) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.

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Publication Details

Published
2025-03-27
DOI
https://doi.org/10.1145/3676641.3715987
Citations
24
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
17.53
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article

Systematic CXL Memory Characterization and Performance Analysis at Scale

Huaicheng Li, Marie Nguyen, Daniel S. Berger, Sam H. Noh et al.
24 citations
CCD and CMOS Imaging Sensors
17.53
article

Systematic CXL Memory Characterization and Performance Analysis at Scale

Huaicheng Li, Marie Nguyen, Daniel S. Berger, Sam H. Noh, Yuyue Wang, Xun Jian, Jinshu Liu, Hamid Hadian
article en
24 citations

Abstract

Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (SPA) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.

Microsoft (United States) (US), University of Washington (US), Samsung (United States) (US), Virginia Tech (US)
Openalex Percentile: Top 1%
CCD and CMOS Imaging Sensors
17.53
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