Systematic CXL Memory Characterization and Performance Analysis at Scale
Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (SPA) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.
Authors
- Huaicheng Li (ORCID: https://orcid.org/0000-0002-3155-0203)
- Marie Nguyen (ORCID: https://orcid.org/0000-0002-7226-1598)
- Daniel S. Berger (ORCID: https://orcid.org/0000-0002-3911-1512)
- Sam H. Noh (ORCID: https://orcid.org/0000-0002-9152-0321)
- Yuyue Wang (ORCID: https://orcid.org/0009-0000-5024-2065)
- Xun Jian (ORCID: https://orcid.org/0000-0002-7120-7426)
- Jinshu Liu (ORCID: https://orcid.org/0000-0002-2490-5176)
- Hamid Hadian (ORCID: https://orcid.org/0000-0002-6160-425X)
Institutions
- Microsoft (United States) (US)
- University of Washington (US)
- Samsung (United States) (US)
- Virginia Tech (US)
Publication Details
- Published
- 2025-03-27
- DOI
- https://doi.org/10.1145/3676641.3715987
- Citations
- 24
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 17.53