Simplifying and Accelerating NOR Flash I/O Stack for RAM-Restricted Microcontrollers
NOR flash has been increasingly popular for RAM-restricted microcontrollers due to its small package, high reliability, etc. To satisfy RAM restrictions, existing NOR flash file systems migrate their functionalities, i.e., block-level data organization and wear leveling (WL), from RAM to NOR flash. However, such fine-grained block-level management introduces frequent index updates and NOR flash scanning, leading to severe I/O amplification, which further deteriorates as they are decoupled in existing NOR flash file systems.
Authors
- Xiangyu Zou (ORCID: https://orcid.org/0000-0001-5104-8301)
- Hongwei Du (ORCID: https://orcid.org/0000-0002-2138-749X)
- Hao Huang (ORCID: https://orcid.org/0009-0009-0826-571X)
- Wen Xia (ORCID: https://orcid.org/0000-0003-4093-6391)
- Yanqi Pan (ORCID: https://orcid.org/0009-0007-7832-0599)
- Liang Shi (ORCID: https://orcid.org/0000-0002-9977-529X)
- Dong‐Jun Yang
Institutions
- Harbin Institute of Technology (CN)
- East China Normal University (CN)
Publication Details
- Published
- 2025-03-27
- DOI
- https://doi.org/10.1145/3676641.3716272
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00