Netlist Feature Extraction for Cmos Analog Circuit Design Warning System

In this paper, a netlist feature extraction is proposed as a part of the analog circuit design warning system. Netlist feature extraction is used to get the information from the circuit netlist to give the netlist recognition and knowledge-based warning system an input for providing a warning or an assistance to the analog circuit designer. The basic component and connection information is extracted in the netlist feature extraction, with additions of new proposed component voltage level feature, current-based circuit splitter and voltage-based circuit splitter. For the simulation and integrity testing, a graph-based netlist recognize system is used with the already fabricated circuit netlist, showing an agreement with the real design.