Rethinking 1T1R architecture and OxRAM stack for memristive neural network inference in-memory

Neural Network hardware in-memory implementations based on memristive synapses are a promising path towards energy efficient Edge computing. Among others, Oxide-based Resistive Random Access Memory (OxRAMs) devices utilization for synaptic weight hardware implementation has shown promising performance on various types of Neural Networks, notably when coupled with bit-error correcting codes or adaptive programming schemes for the device intrinsic variability management. In this context, memristive footprint reduction coupling with Multi-Level-Cell (MLC) operation remains essential to hardware implement highly accurate state-of-art Neural Networks, whose number of parameters is exponentially increasing over time. In this work, a compact OxRAM-based 1 Transistor – 1 Resistor (1T1R) architecture, where the memory is integrated inside the 40 nm × 40 nm drain contact of thin-gate oxide FDSOI transistors, is demonstrated in 28 nm technology. The memory structure is optimized from the OxRAM active material level to the cell architecture. This results in 10 6 endurance and 11-level MLC encoding resilient to 10 9 inference cycles compatible with 0.0357 μm 2 bitcell footprint potential in 28 nm technology. Altogether, the proposed 1T1R cell density is competitive with respect to ultra-dense 1S1R-based Crossbar arrays, while being compatible with in-memory Neural Network inference implementations on-chip.