A Low-Power Receiver Equalization Circuit Based on Source Degeneration Structure

In the SerDes high-speed serial communication system, in order to eliminate the impact of non-ideal characteristics such as reflection, crosstalk and jitter, it is necessary to introduce an equalization circuit in the system to eliminate losses such as inter-code crosstalk. SerDes is often used in a variety of protocols, including high-speed protocols and low-speed protocols. In the case of low-speed protocols, we often use DFE plus CTLE structure, which consumes a lot of power. To address this problem, this paper proposes a low-power structure receiver equalization circuit. This circuit is based on the UMC28nm CMOS process. This circuit structure consists of three first-level traditional non-adjustable CTLEs, a two-level CTLE and a current mode structure weighted circuit. The non-adjustable CTLE structure is used for fixed gain equalization adjustment, and adaptive adjustment is achieved by adjusting the current copied by the current mirror in the current mode structure. Compared with the traditional adaptive CTLE structure, the adjustable resistor and capacitor array are reduced, which greatly reduces power consumption.