Design of a Gate-Diode LVTSCR with High Holding Voltage and Robustness

A gate-diode LVTSCR(GDLVTSCR) is proposed and implemented in 0.18um CMOS technology. By embedding a gate-diode in the traditional LVTSCR, an additional surface discharge path is provided, thereby enhancing the holding voltage and robustness. Transient simulations of the device were carried out using TCAD, the turn-on process and working principle of the device were analyzed. The simulation results demonstrate that the gated diode path can discharge the large ESD current together with the main SCR. The TLP test results demonstrate that compared with traditional LVTSCR, the proposed GDLVTSCR has a lower |V|<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</inf>, a higher |V|<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</inf>, and a greater failure current.