An Optimization Method for Placement of Analog Integrated Circuits Based on Reinforcement Learning with Routing Collaboration

Placement and routing, as pivotal aspects of the physical design process in analog integrated circuit(IC) design, have encountered numerous new constraints and challenges amid the recent rapid advancements in analog IC technology. Over the past several decades, substantial research has been conducted on analog IC Placement algorithms, yielding many groundbreaking achievements. However, traditional studies often treated placement and routing as two relatively independent steps in the optimization process. The majority of placement methods, including Simulated Annealing(SA) and Genetic Algorithms(GA), focused on optimizing placement through rigid evaluation metrics such as half-perimeter and overlapping area. This approach holds the potential to generate placements that may seem optimal at first glance but exhibit subpar routability, subsequently influencing the chip's performance, placement dimensions, reliability, power consumption, and yield. In practical production, there is an inseparable connection between placement and routing, and the quality of routing results can be utilized to assess the merits of the placement . To some extent, the purpose of placement is to align routing more closely with design rules. Hence, leveraging reinforcement learning, we have developed an optimization methodology for the placement of analog IC, emphasizing the synergy between placement and routing. Our devised approach departs from conventional placement methods bound by stringent metrics; instead, we directly evaluate the placement's efficacy based on its practical routing capabilities. Experimental findings from a multitude of real-world designs illustrate that even minute adjustments to the placement , within our method, yield superior final placement designs, ultimately achieving enhanced routability.