A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate

Threshold Logic Gate (TLG) has gained attention with the emergence of novel technologies such as memristors. TLG offers improved performance and lower power dissipation while occupying less silicon area. This paper introduces a novel dynamic clock generator circuit that further enhances TLG performance. The proposed circuit replaces the NAND gate-based approach used for clock generation in differential TLG implementations. It reduces the propagation delay of the TLG while reducing its static power dissipation, an important factor in energy-efficient circuit design. Simulations indicate up to a 25% reduction in delay compared to the NAND gate-based approach. Furthermore, the proposed circuit occupies 45% less area than the NAND gate. These findings highlight the potential of the proposed dynamic clock generator for advanced threshold logic implementations, paving the way for further innovations in the field.