A Tiny Processor with Rapid Interrupt Response for AI Accelerator Control

This paper presents the design and implementation of an ultra-compact RISC-V–based processor optimized for low power consumption, minimal size, and rapid interrupt response, specifically targeting the control of AI accelerators. The proposed processor incorporates two key innovations: a simplified architecture for managing external IPs and a dedicated fast interrupt response controller. These features result in a streamlined core and reduced interrupt handling latency, making the processor highly suitable for real-time applications such as embedded AI systems and edge computing. The rapid interrupt response mechanism ensures that external interrupts are handled within four clock cycles for non-nested interrupts and non-jump instructions. When implemented on an FPGA, the proposed processor reduces hardware overhead compared to picoRV32, achieving a 20.7% decrease in Slice LUTs and a 27.9% reduction in Slice Registers. Simulation results using the CMOS 65nm process demonstrate a 31.7% reduction in area and a 26.7% decrease in power consumption, while task execution efficiency is only reduced by 1.68%.