Design of Optimized Carry Select Adder (OCSA) for Low-Power IoT Applications

This work demonstrates the design of a low-power circuit for Internet of Things (IoT) applications. Most of the IoT and embedded applications relies on battery powered devices and executes high-speed computation. Hence, power constraints are critical. Adders are the crucial component for any computation unit. Thus, the design of low-power and high-speed arithmetic processing units are in growing demand for extended battery life and efficient computation in IoT devices. In this paper we proposed the architecture of a Carry Select Adder (CSA) optimized to reduce power and propagation delay. The architecture employs MDCVSL (Modified Differential Cascode Voltage-Switch Logic) as a Mux to realize efficient computation and minimum Power-Delay Product (PDP). The proposed Optimized Carry Select Adder (OCSA) architecture is implemented in Cadence Virtuso using GMDK 90 and the result shows that it improves power and propagation delay by a factor of $\mathbf{2 0 \%} \& \mathbf{1 0 . 5 2 \%}$ respectively.