A Continuous Ramp Generator Design for Column-Parallel CMOS Image Sensors Utilizing Novel Row-wise Noise Suppression Techniques

This paper presents a novel continuous ramp generator designed for single-slope ADC (SS-ADC) architecture CMOS image sensors (CIS), with the aim of reducing row-wise noise. Based on traditional continuous ramp generators, two additional sampling capacitors are used to reduce the noise in the ramp reset voltage and the integration current, which can cause irregular horizontal stripes in images, especially in low-light conditions. By employing digital correlated double sampling (DCDS) techniques, the sampling capacitors sample the reset voltage and the current source bias voltage before the ramp voltage rises, ensuring that the conditions for generating the two ramp voltages are essentially the same, thereby suppressing the impact of noise fluctuations on the count value. Through the fabrication and testing of a CMOS image sensor using 350nm/55nm process, the proposed method has been proven to reduce row noise by 80%, demonstrating excellent row noise suppression performance.