Comparative Analysis of Standard Ternary Inverter Architectures based on 18nm FinFET Technology

As modern VLSI circuits encounter growing challenges in power consumption and interconnect complexity, ternary logic emerges as a promising alternative to traditional binary logic by introducing a third logic state. This enhancement enables higher data density and more efficient circuit designs, significantly reducing the number of interconnections and gates required. This research aims to evaluate and compare the performance of three FinFET-based ternary inverter architectures by analyzing key metrics such as power consumption, propagation delay, and power-delay product (PDP). Using simulations conducted in the Cadence Virtuoso tool, the study reveals that the design proposed in [14] excels in power efficiency, while the design in [13] achieves a lower propagation delay. The findings highlight the potential of ternary logic, combined with FinFET technology, to improve energy efficiency and performance in future VLSI circuits, making it well-suited for low-power and high-speed applications.