A Novel Power-Gating 8T SRAM Cell with Improved Standby and Operational Efficiency

This paper introduces a groundbreaking static random-access memory (SRAM) cell, termed the Power-Gated 8T (PG8T). The innovative design integrates a read-decoupled access buffer and power-gating transistors, collaboratively enhancing the reliability of data read and write operations. A standout feature of the PG8T SRAM cell is its ability to operate efficiently at an ultra-low voltage of 0.32V. Our proposed PG8T SRAM design provides a comprehensive comparative analysis of design metrics across various SRAM architectures, including 9T, 8T, and PG9T SRAM cells. Through detailed simulations, key design parameters—such as hold power, write power, read power, RSNM, read delay and write delay—are meticulously evaluated and summarized. The results demonstrate that the our PG8T SRAM cell significantly outperforms as compared to traditional SRAM cells in terms of power efficiency, achieving substantial reductions in hold power, and write power, often by several orders of magnitude. Higher RSNM value of simulated result of PG8T as compared to other SRAM cell showing better stability and lower read/write delay showing fast performance. These findings underscore the potential of energy-efficient SRAM configurations for low-power applications, paving the way for advancements in sustainable electronic systems.