Clock Domain Crossing Aware RTL Synthesis using Fusion Compiler in Commercial Display Chip Design

As the performance requirements of display chips increase, less area, less power consumption, good performance display chip become more critical factors for LCD panel manufacturer. So this puts a lot of demands on chip development. Chip designer need speed up the chip development iteration rate. There are many methods to achieve this goal by the way introduce new problem. For example, to get better performance design house will use same RTL code do process transfer. But same RTL may not suitable in timing aspect for difference design process. RTL designer use high level Synthesis tool create RTL more fastly. Some company may purchase soft encrypted RTL IP from IP vendor. But high level synthesis rtl & encrypted rtl make RTL design unreadable. It increase clock domain crossing risk during design optimization. These give more challenge for design synthesis & implementation engineer. Fusion Compile (FC) is an EDA tool from Synopsys. It combined synthesis stage and place route. Make implementation step more efficiency. More compact implementation method speed up design cycle. More ever It make design timing closure more easily and get good power area. Design house can use this tool achieve difficult design goal. We present a fusion compile design flow. To solve clock domain crossing issue in implementation design stage and apply this flow for one of arithmetic block in commercial display chip. Get good optimize results avoid any clock domain crossing risk.