Secure Federated Learning for Gate-Level IP Hardware Trojan Detection Using Homomorphic Encryption

The globalization of pre-silicon to post-silicon transformations in smart circuits through third-party EDA toolchains introduce security challenges, particularly the risk of hardware Trojans (HT). Most existing HT detection methods rely on binary classification models to detect the presence of HTs in pre-silicon Intellectual Property (IP). This paper presents a novel approach to Design-for-Hardware-Trust (Dfht), leveraging machine learning (ML) to predict HT presence with enhanced accuracy. We introduce a federated learning framework using homomorphic encryption to ensure data privacy and security, training HT detection models on decentralized gate-level IP datasets. Compared to the existing untrusted training infrastructure, sensitive information associated with the HT dataset remains unexposed to the proposed federated cloud server. The Synthetic Minority Oversampling Technique (SMOTE) is applied for data preprocessing to address class imbalance. Our federated-learning-enabled Dfht approach improves IP quality, testability, and security, effectively countering ML-activated hardware back-doors. Experimental results demonstrate the effectiveness of this method in maintaining HT-free designs.