FPGA Implementation of Velocity Estimation Method Using Chebyshev Expansion

In motion control, velocity is required to be estimated with less delay and less error, but the two are trade-offs because of an encoder's quantization noise, and they are difficult to make both small simultaneously. This paper aims to overcome the trade-off when conventional methods are used. This paper proposes an FPGA (Field Programmable Gate Array) implementation method for a model-free velocity estimation using Chebyshev expansion. The use of Chebyshev expansion enables better rejection of quantization noise from the measured data than using a frequency-domain filter. The estimation method is realized by a single inner product calculation, which takes 3μs of computation time on FPGA. The performance of the proposed method is validated by a velocity estimation from actual encoder data.

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Publication Details

Published
2025-02-28
DOI
https://doi.org/10.1109/icm62621.2025.10934937
Citations
1
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
2.27
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FPGA Implementation of Velocity Estimation Method Using Chebyshev Expansion

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FPGA Implementation of Velocity Estimation Method Using Chebyshev Expansion

Wataru Ohnishi, Yusuke Nomura, Takafumi Koseki, Shuji Takada, Adiyasuren Altanbileg, Kosuke Numata
article en
1 citations

Abstract

In motion control, velocity is required to be estimated with less delay and less error, but the two are trade-offs because of an encoder's quantization noise, and they are difficult to make both small simultaneously. This paper aims to overcome the trade-off when conventional methods are used. This paper proposes an FPGA (Field Programmable Gate Array) implementation method for a model-free velocity estimation using Chebyshev expansion. The use of Chebyshev expansion enables better rejection of quantization noise from the measured data than using a frequency-domain filter. The estimation method is realized by a single inner product calculation, which takes 3μs of computation time on FPGA. The performance of the proposed method is validated by a velocity estimation from actual encoder data.

Astronomical Society of Japan (JP), The University of Tokyo (JP)
Affordable and clean energy
Openalex Percentile: Top 17%
Embedded Systems Design Techniques
2.27
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