Design and application of error-compensated approximate multipliers

In the context of the rapid development of electronic information technology, the rapid progress of emerging technologies such as the Internet of Things, big data analysis and artificial intelligence has posed unprecedented performance and power consumption challenges to computing systems. In many compute-intensive applications, completely accurate calculations are not always necessary. These applications tend to tolerate a certain level of calculation error. Therefore, it is a very effective idea to use approximate calculations and introduce errors in exchange for performance and power optimization. This thesis focuses on the study of approximate Booth multipliers and proposes a new approximate multiplier structure Approximate Error-compensated Booth Multipliers (AEBM), designed with error compensation. This includes an approximate Booth encoder, a newly proposed approximate 3-2 compressor and 4-2 compressor, and an approximate partial product array with error compensation based on the division of approximate factors. Compared to the structure discussed in [1], the key hardware performance indicator PDP of the AEBM structure is only 50.3%, and NMED is only 53.4%. Compared to [2], the PDP of the AEBM structure is 94%, and NMED is 1.4%, achieving a comprehensive design of accuracy and hardware performance. Finally, when applied to a neural network for image denoising, AEBM outperforms other approximate multipliers in terms of PSNR and SSIM. Compared with the exact multiplier, PSNR only loses 0.4, SSIM only loses $\mathbf{0. 0 1 5 8}$.