Thermal stress behavior and optimization of solder joints in CSP-LED packages

• A novel FEA-Taguchi framework optimizes CSP-LED solder joint reliability. • Anand viscoplastic modeling reveals critical stress localization in CSP-LED packages. • PCB material significantly impacts thermal stress behavior and solder joint durability. • Optimal design (0 % void ratio, GaN substrate, 40 μm solder layer, ceramic PCB) enhances reliability. • Findings contribute to improved thermal management strategies for high-power LEDs. This study explores the thermal stress behavior of chip-scale LED (CSP-LED) packages with a focus on micro/nanoscale interfacial effects and thermal transport under rapid temperature cycling. Finite element analysis (FEA), combined with advanced Taguchi optimization, identifies critical stress zones and evaluates the impact of void ratio, chip substrate material, solder layer thickness, and PCB substrate material on solder joint reliability. Results reveal that maximum equivalent stress concentrates at the solder layer's outer corners due to thermal mismatch. Key findings include the dominant role of PCB substrate material and microstructural void configurations in affecting interfacial stress. Optimal conditions, such as a void ratio of 0 %, a ceramic PCB, and a 40 μm solder layer, significantly enhance mechanical reliability. These insights contribute to advanced thermal management strategies for CSP-LEDs and other high-power electronics.