A low-power, high-efficiency charge pump circuit for the coexistence of multiple charge pumps in 55 nm CMOS

In intelligent mobile devices, a memory circuit is one of the important modules, charge pump circuit can provide the necessary high voltage for memory. This paper presents a charge pump circuit fabricated in the SMIC 55 nm BCD CMOS process to improve the working efficiency and reduce the power consumption of the circuit. The charge pump circuit designed in this paper takes into account the bulk effect of the transistor, and employs a dynamic substrate bias circuit in combination with a transmission transistor to eliminate the impact of the bulk effect on the threshold voltage; the clock circuit generates the staggered phase clock with double voltage output, reduces the influence of threshold voltage, and improves the working efficiency of charge pump circuit. Compared with the traditional charge pump circuit, this paper also considers the problem of excessive peak-to-peak current caused by multiple charge pumps working simultaneously. This article enables different charge pump circuits to be alternately turned on, to reduce the transient power consumption of the charge pump start; flip-flops capture and generate charge pump feedback clocks with different phases, reducing power consumption during the dynamic stabilization phase of the charge pump. Simulation results show that the charge pump circuit designed in this paper can meet the requirements of low power consumption and high efficiency when multiple charge pumps work simultaneously.