Design of a Level-1 Data Cache for the Processor Based on Single Instruction Multiple Threads

This paper presents the design and Verilog implementation of a Level-1 data cache targeting the high-concurrency memory access requirements of a custom-instruction-set SIMT architecture processor. By introducing a multi-bank architecture and a row interleaving strategy, consecutive cache lines are distributed across different banks, effectively exploiting data locality among concurrent threads in the SIMT processor. The design of the Miss Status Handling Register (MSHR) supports non-blocking execution in the custom-instruction-set SIMT processor, adopting content-addressable memory and dual-issue two-stage pipelines. In Verilog RTL simulation tests based on convolutional neural network workloads using the custom instruction set, the data cache consistently reduces data transfer latency and improves overall processor performance across various configurations.