Design and Optimization of a Novel LVTSCR Triggered SCR Device for 5-V Applications

The conventional low voltage triggered silicon-controlled rectifier (LVTSCR) has a relatively low holding voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</inf>), so it is susceptible to latch-up risks when the operating voltage is 5 V. In this paper, we studied a modified electrostatic discharge protection device called LVTSCR triggered SCR (LVTSCRTSCR), which consists of the conventional LVTSCR on one side and the conventional SCR structure on the other side. To further enhance the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</inf> of LVTSCRTSCR, we designed a new device named ILVTSCRTSCR, which has an embedded parasitic NPN transistor based on the LVTSCRTSCR. These devices were all developed in a 0.18 μm CMOS technology, and their operation mechanisms were explored and analyzed by TCAD simulations. In addition, these devices have been verified by the TLP testing system. The results show that compared to the conventional LVTSCR, the ILVTSCRTSCR has a higher V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</inf>. By further optimizing a crucial structure parameter of the ILVTSCRTSCR device, the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</inf> could exceed 5.5 V. Consequently, the ILVTSCRTSCR is a prospective ESD protection device for 5 V I/O.