Designing an Enhanced APUF Structure Optimized for FPGA Implementation

With the rapid advancement of the semiconductor field, hardware security has become increasingly critical. Physical Unclonable Functions (PUFs), due to their unclonable and unpredictable characteristics, have emerged as a promising solution in hardware security applications. However, as technology progresses and research on attacks against PUFs deepens, the susceptibility of PUFs to modeling attacks has become evident. This paper proposes a novel obfuscation scheme that utilizes the original inputs and outputs to control key selection, thereby obfuscating the mapping between challenges and responses. This approach signifivantly enhances the resistance of PUFs to machine learning-based modeling attacks. The proposed design has been successfully implemented on an FPGA. Experimental results show that the proposed PUF structure achieves high reliability, uniformity, and randomness while effectively resisting a range of common machine learning attack methods.