Cryo-CMOS Model-Enabled 8-bit 32 MS/s SAR ADC with Split Capacitor Array

This article presents a cryogenic 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using Nexchip 110 nm 1P6M CMOS technology for the readout of qubits. To mitigate the base freeze-out effect of bipolar junction transistors at cryogenic temperature and the resulting unavailable BJT-based bandgap voltage reference circuits, a VCM -based switching procedure through a capacitive DAC with top-plate sampling split capacitor array was employed. By the adoption of compact cryo-CMOS SPICE model and asynchronous control logic, the ADC achieves an SNDR of 41.56 dB and consumes 2.1 mW while maintaining the Walden FoM of 646 fJ/conv.-step at 4.2 K and 32 MS/s. The converter occupies an active area of 0.106 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.